资讯

Design And Reuse1 天
Cadence Launches Cache-Coherent HiFi 5s SMP for Next-Gen Audio Applications
Amid this rapidly evolving landscape, an out-of-the-box hardware design with multicore-enabling operating software is needed to reduce hardware design time and tame the software complexity of ...
Design And Reuse1 天
True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.
Design And Reuse2 天
How Arasan s SoundWire PHY Can Elevate Your Next Audio SoC
If your next SoC needs a robust, power-efficient, and real-time audio interface, Arasan’s SoundWire PHY is the ideal ...
Design And Reuse6 天
InCore Unveils SoC Generator Platform: From Idea to FPGA Validation in Minutes ...
InCore Semiconductors, a fabless semiconductor startup, today announced a major milestone with the successful silicon ...
Design And Reuse15 天
Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry's ...
Coupled with our Silicon Lifecycle Management IP, OEMs can assess real-time silicon health metrics such as voltage, temperature, and margins. They can also monitor silicon aging and reliability across ...
Design And Reuse3 天
Why Hardware Security Is Just as Critical as Software Security in Modern Systems
Hardware security — implemented at the silicon level across processors, storage components, input/output devices, and power supplies — and software security play distinct roles and have unique ...
Design And Reuse8 天
Powering the Future of RF: Falcomm and GlobalFoundries at IMS 2025
Falcomm is proudly U.S.-based, and all products are fully designed and manufactured domestically, including products ...
Design And Reuse2 天
CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications
Woodcliff Lake, New Jersey — June 19, 2025 — Semiconductor intellectual property core provider CAST has introduced a new direct memory access (DMA) IP core that alleviates a system’s host CPU from the ...
Design And Reuse12 天
Transition Fixes in 3nm Multi-Voltage SoC Design
Transition or slew is the delay taken by a signal to rise from logic “0” to “1” or to fall from logic “1” to “0”. Transition ...
Design And Reuse2 天
PCIe 7.0 Keeps Pace with AI Demands
Aimed at AI, cloud and data center environments, the Optical Aware Retimer Engineering Change Notice amends the PCIe 6.4 specification and the new PCIe 7.0 specification to include a PCIe ...
Design And Reuse3 天
CEA-Leti and Soitec Announce Strategic Partnership to Leverage FD-SOI for Enhanced Security ...
CEA-Leti and Soitec today announced a strategic partnership to enhance the cybersecurity of integrated circuits (ICs) through the innovative use of fully depleted silicon-on-insulator (FD-SOI) ...
Design And Reuse2 天
Sustainable semiconductor manufacturing - too little too late or Europe protectionism?
58 companies and research organisations across Europe have come together in a €55m programme to boost the sustainability of producing semiconductor devices. From energy and water use to the gases and ...