A 32-bit single-cycle MIPS processor implemented in structural VHDL. Supports basic arithmetic, logic, memory, and control flow instructions. Designed and tested using QuestaSim and MARS for ...

This project implements a custom 34-bit multi-cycle CPU using SystemVerilog. The CPU supports a simple instruction set architecture (ISA) and simulates the execution of a loop summation program (sum = ...

Abstract: As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limited set of datapath units. By utilizing a flexible datapath interconnect and a wide control ...

Abstract: We present, in this paper, a framework supporting a formal verification of UML diagrams using the Maude language. The approach considers both static and dynamic features of object-oriented ...

The processors will be implemented using Virage Logic’s silicon-proven IPrima Foundation™ Platform IP and will target SMIC’s 130-nanometer (nm) process technology. “Tensilica’s new Diamond ...

LSI Logic's unique ECC Memory Protection core provides cost-effective soft error protection for the tightly coupled memories of the ARM9 and ARM11 family of ...