This project focuses on implementing an RTL design of an AHB to APB bridge comprises of AHB slave interface, state machine and APB interface, including simulation of read and write operations.

The Joules RTL Design Studio delivers up to 5X faster RTL convergence, 25% improved QoR, precise physical insights, and actionable guidance for RTL. Cadence Design Systems, Inc. has launched the ...

RTL Design Engineer for DDR Memory Controller IP development team. The position is based in Bangalore. The role would include the design and support of the RTL of the DDR Memory Controller solution of ...

A Simulator is a tool for checking the RTL design which is designed according to the given specifications. In this workshop we used a open-source simulator called iVerilog for the design simulations.