Charlie Su will explain the rich portfolio of AndesCore™ RISC-V processor IPs already populating these SoCs: compact single-issue cacheless cores to feature-rich Linux-capable superscalar cores, cache ...

Enter T1 (short for Torrent-1), a RISC-V vector inspired by the Cray X1 vector machine. T1 has support for features, including lanes and chaining. The chip contains a version of the Rocket Core ...

It is a real-time high-performance DSP IP, which can boost the performance of voice, audio, video, image and AI processing. Its “F” extensions support IEEE 754-compliant single precision floating ...