You can run the full suite of tests by executing make test in the directory you used to build Scanner ... If you use Scanner in your research, we'd appreciate it if you cite the paper with the ...

Abstract: In this paper we present a novel approach to delay-testing of VLSI logic chips based on the level-sensitive scan design (LSSD) methodology. The objective of the delay test is to reduce ...

This paper describes the LSSD logic structures required, the reduced-pin-count testing and burn-in processes used, and the ASIC product design decisions that must be made to establish a consistent ...

Other papers demonstrate the enormous potential of using scanner data to test economic theories and estimate the parameters of economic models, and provide solutions for some of the problems that ...