Design-Reuse3 天
FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
The FPD LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Data Enable, and Pixel Clock to a FPD LVDS compliant display panel via 3 or 4 ...
GitHub3 天
README.md
libxcvt is a library providing a standalone version of the X server implementation of the VESA CVT standard timing modelines generator. $ git clone https://gitlab ...
Design-Reuse3 天
TSMC LCD Controller IP Core
The Digital Blocks DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protocol Interconnect to a LCD or OLED display panel. ... The ...