News

EDN21y
SystemC tool ‘automates’ ESL-to-RTL design flow
SANTA CRUZ, Calif. — Offering technology that it claims will automate the electronic-system-level (ESL) to RTL design flow, startup SpiraTech Ltd. has announced Cohesive, a tool set that bridges ...
EDN21y
RTL design handoff is ready
Recent design-tool and methodology enhancements, such as physical synthesis and unified RTL-to-layout tools and design flows, do not solve the problems of wasted time and money during complex chip ...
Electronic Design24y
RTL Design Verification Tool Eliminates Learning Curve
By providing verification early in the design cycle to find as many RTL problems as possible, users of the verification tool can formally check assertion monitors to find deeply embedded bugs.
EE Herald12y
Tool compare synthesizable RTL codes without testbenches or simulation vectors
“Our formal verification solutions now span the entire SoC design project and can be used by system ... schematic and driver/load tracing. The tool can be used to revise IP and RTL code and to compare ...
Verdict on MSN1d
Synopsys gets conditional FTC approval for Ansys acquisition
As per the latest conditions set forward by the FTC, the companies must divest certain assets to Keysight Technologies to ...
Electronic Design21y
An Easier Path To RTL For DSP Algorithms
Not only does the tool produce RTL code for a given DSP design, it also creates a testbench. The generated RTL model can be verified using any HDL simulator that uses the stimulus from the ...
EE Herald12y
VLSI design tool identifies critical issues in RTL phase of ASIC and FPGA designs
Aldec has released VLSI design tool ALINT 2012.12, a static design analysis and checking tool to identify critical issues early in the RTL design phase of ASIC and FPGA designs. ALINT 2012.12 features ...
Design-Reuse23y
IP Verification : RTL prototyping: a hardware/software co-verification solution
supports optimized hardware/software implementations and allows real-world stimulus for early-stage software design and debug. FPGA-based RTL prototyping delivers these advantages for both hardware ...
Semiconductor Engineering11y
RTL Design-for-Power In Mobile SoCs
Power consumption is a key mobile concern both from a hardware and software standpoint and is addressed during all aspects of the design. This discussion focuses on Register Transfer Language (RTL) ...
Design-Reuse14y
Power analysis of clock gating at RTL
As shown in Figure 9, advanced power reduction tools like SpyGlass-Power can not only find new enable opportunities for the original implementation, but also fix the RTL design automatically. These ...
Semiconductor Engineering7y
Tools To Design CNNs
Those designs also can leverage standard tooling from RTL on down. But there is a mindset ... to the chip and system designers. Second, enhanced tools are in the works that both enable design of CNNs ...