资讯

EDN21 年
SystemC tool ‘automates’ ESL-to-RTL design flow
SANTA CRUZ, Calif. — Offering technology that it claims will automate the electronic-system-level (ESL) to RTL design flow, startup SpiraTech Ltd. has announced Cohesive, a tool set that bridges ...
Design-Reuse15 年
Sequence Launches PowerArtist-XP - Industry's First Automatic, Fully Integrated RTL Design ...
“Power management is a top priority and Sequence’s PowerArtist-XP is a key tool we use for power efficient RTL design flows,” said Jiebing Wang, Vice President of Acceleration Technology at Exar ...
Electronic Design11 年
Hybrid Emulation Accelerates Architecture Optimization, Software Development, And Software ...
Before the new RTL-based (register transfer level) platform is available, key design decisions can be evaluated to ensure performance and other specifications are met. Software developers can use ...
Design-Reuse14 年
Power analysis of clock gating at RTL
As shown in Figure 9, advanced power reduction tools like SpyGlass-Power can not only find new enable opportunities for the original implementation, but also fix the RTL design automatically. These ...
EDN21 年
RTL design handoff is ready
Designers need more comprehensive up-front analysis and earlier visibility into the physical effects of the design. Recent design-tool and methodology enhancements, such as physical synthesis and ...
EE Herald12 年
VLSI design tool identifies critical issues in RTL phase of ASIC and FPGA designs
Aldec has released VLSI design tool ALINT 2012.12, a static design analysis and checking tool to identify critical issues early in the RTL design phase of ASIC and FPGA designs. ALINT 2012.12 features ...
EE Herald12 年
Tool compare synthesizable RTL codes without testbenches or simulation vectors
equivalence checking software that compares revisions of register transfer level (RTL) code. 360 EC-RTL is part of the OneSpin 360 EC Product Family. An RTL-to-RTL equivalence checker features ...
Electronic Design24 年
RTL Design Verification Tool Eliminates Learning Curve
By providing verification early in the design cycle to find as many RTL problems as possible, users of the verification tool can formally check assertion monitors to find deeply embedded bugs.
Semiconductor Engineering11 年
RTL Design-for-Power In Mobile SoCs
Power consumption is a key mobile concern both from a hardware and software standpoint and is addressed during all aspects of the design. This discussion focuses on Register Transfer Language (RTL) ...
mccormick.northwestern.edu9 年
COMP_ENG 355: ASIC and FPGA Design
and develop the skills necessary to solve critical digital design problems efficiently. Using commercial CAD tools, you will learn how to implement RTL VHDL designs, verify your application through ...
CU Boulder News & Events4 年
FPGA Design for Embedded Systems Specialization
You will cover a variety of topics, including Verilog, VHDL, and RTL design for FPGA and CPLD architectures; FPGA development tools flow; configurable embedded processors and embedded software; the ...