Design-Reuse1 个月
Digital Design with RTL Design, VHDL and Verilog, Second Edition IP Listing
The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to a TFT LCD panel. In an FPGA, ASIC, or ASSP ...
Design-Reuse18 天
Digital VLSI design flow rtl netlist IP Listing
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is ... via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / ...