You also need to add new code to the instruction set simulator. Finally, RTL must be extended, and any changes to the RTL must be verified. Depending on the amount of manual effort, ISA extensions can ...

Electra IC Advanced Verification Suite (EAVS) for RISC-V Cores is a powerful and flexible RISC-V core verification environment. It integrates a UVM testbench, Instruction Set Simulator (ISS), and ...