Frontiers5 年
Single-Cell Electrical Stimulation Using CMOS-Based High-Density Microelectrode Arrays
Here, we investigated single-neuron current and voltage stimulation in vitro using high-density microelectrode arrays featuring 26,400 bidirectional ... Electrical stimulation was controlled via an on ...
IEEE2 年
Design Considerations in HighTemperature Analog CMOS Integrated Circuits
Tbe design of CMOS analog integrated circuits to ... successfully been implemented in tbe design of basic analog cells for operation over the 25°-250° C range are empbasized. Simple models are ...
GitHub2 年
Four-Quadrant CMOS Analog Multiplier
[1] B. Gilbert, “A high-performance monolithic multiplier using active feedback,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 364-373, Dec. 1974. [2] SHI-CAI QIN ANDRANDY L. GEIGER, A +-5-V CMOS ...
Design-Reuse8 年
SST and SilTerra Announce Production Readiness of Embedded SuperFlash Macros on SilTerra's ...
(NASDAQ: MCHP), a leading provider of microcontroller, mixed-signal, analog ... s 180 nm CMOS technology. The off-the-shelf macros allow SilTerra customers access to SST’s unique SuperFlash ...
GitHub2 年
Systematic Design of Analog CMOS Circuits
Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs ...
Design-Reuse6 年
SST and UMC Announce Qualification of Embedded SuperFlash Technology on 40 nm CMOS Process
April 30, 2018 -- The amount of data processed in Internet of Things (IoT) applications continues to increase, making low power and high density paramount to system designers. Many IC designers are ...
IEEE1 年
Xirui Du
Energy Efficiency,High Energy Efficiency,Analog-to-digital Converter,Area Overhead,Convolutional Neural Network,Density Data,Neural Network,Object Detection,Ultrahigh Density,65-nm CMOS,Adder ...
Electronic Design1 个月
Graphene-Based Interconnects Could Improve Density of Digital, Analog, and Power ICs
A new process for creating interconnects on ICs using high-conductivity 2D graphene films ... process conditions used to fabricate standard CMOS devices. The process, known as CoolC GT300, enables ...