The AES Coprocessor encrypts and decrypts 128-bit data blocks by computing an AES algorithm with a 128, 192 or 256-bit key through a highly secure architecture (SPA, DPA[1] and fault hardened).

The family of IPX-AES IP-Cores provides an efficient FPGA implementation of the Advanced Encryption Standard (AES). Its flexibility allows the combination ... fields with a design architecture that ...

Panel remote uploading/downloading via Internet Programmable using DLS 5 or keypad Supervision heartbeat via Internet 128 Bit AES Encryption Full event reporting SIA and Contact ID protocol (System 5 ...

Integrated call routing. Panel remote uploading/downloading support via GPRS and Internet. Supervision heartbeats via GPRS and Internet. 128-bit AES encryption via GPRS and Internet. Full event ...